基于失效物理的集成电路故障定位方法

Fault Localization Method for ICs Based on the Failure Physics

超大规模集成电路后道工艺(BEOL)中的失效日益增多,例如多层金属化布线桥连、划伤,栅氧化层的静电放电(ESD)损伤、裂纹等失效模式,由于失效点本身尺寸小加上电路规模大,使得失效分析难度增加。为了能够对故障点进行快速、精确定位,提出了基于失效物理的集成电路故障定位方法。根据CMOS反相器电路的失效模式提出了4种主要故障模型:栅极电平连接至电源(地)、栅极连接的金属化高阻或者开路、氧化层漏电和pn结漏电。结合故障模型产生的光发射显微镜(PEM)和光致电阻变化(OBIRCH)现象的特征形貌和位置特点,进行合理的失效物理假设。结果表明,基于该方法可对通孔缺陷、多层金属化布线损伤以及栅氧化层静电放电损伤失效进行有效的定位,快速缩小失效范围,提高失效分析的成功率。

Failures in the back end of line(BEOL) of very large scale integration(VLSI) have become more and more, such as the multilayered metallization bridge/scratch defect, gate oxide layer electrostatic discharge(ESD) damage and rupture defect. Since the failure site is tinier and the circuit scale is becoming larger, failure analysis is more difficult than before. The fault localization method for the integrated circuit based on the failure physics was proposed,in order to make a quick and precise fault loca-lization of the defect. According to the failure modes of inverters in CMOS ICs, four main fault models were proposed. Those were abnormal resistive path of gate to VDD(or GND), high resistive path or open of gate, gate oxide leakage and pn junction leakage. The signature and location of photon emission microscopy(PEM)and optical beam induced resistance change(OBIRCH) spots generated by these failure modes were studied, by which a proper failure physics was suggested. The results show that the via defect,the electrical damage of multilayered metallization and ESD failure of gate oxide can be successfully localized based on the method. The failure spot is narrowed down quickly and the successful rate of failure analysis is also improved by the method.