基于28nm工艺的CCOpt技术高效时钟树设计

Design of efficient clock tree by CCOpt technology for 28 nm process

为了设计合理高效的时钟树网络,对建立和保持时间约束以及时钟偏差进行分析,基于28 nm工艺设计了一款高速数字芯片,采用Innovus工具实施布局布线,在时钟树综合(CTS,clock tree synthesis)阶段采用CCOpt(clock concurrent optimization)技术,合理利用时钟偏差,同时优化时钟路径和逻辑路径,对时钟网络进行优化,并考察时钟树延时、时序和时钟网络功耗等指标。结果标明:与传统CTS技术相比,采用CCOpt技术时,最差时序违例和违例路径数量减少50%;布局布线时间减少2 h;芯片时钟网络内部互连功耗减少55%,泄漏功耗减少80%,有效提高了数字芯片的性能。

In order to design a reasonable and efficient clock tree network,the constraints of setup and hold time and the clock skewing were analyzed.A high digital chip was designed based on the 28 nm process.The Innovus tools were used to implement layout and wiring.In the clock tree synthesis(CTS)stage,the CCOpt(clock concurrent optimization)technology was used to optimize the clock network through the reasonable use of clock skewing and the simultaneous optimization of clock path and logic path.The indexes including the clock tree delay,time sequence,and power consumption of clock network were analyzed.The results showed that compared with the traditional CTS,the worst negative slack and the number of violations path was reduced to 50%by CCOpt technology.What′s more,the time of layout and wiring was reduced by two hours,the inter connect power consumption of clock network was reduced by 55%and the leakage power consumption was reduced by 80%.The performance of digital chip was improved effectively.