摘要
讨论在标准0.18μm CMOS逻辑平台上加入一次性编程单元(OTP Cell)后,工艺所面临的问题。由于OTP Cell的设计尺寸远小于0.18μm技术代的设计要求,导致用传统工艺对OTP Cell中具有高纵横比的间距进行填充时,会出现空洞。该空洞贯通前后接触孔(CT),使得后续在沉积TiN时,TiN会残留在空洞侧壁上,使相邻接触孔短路,从而导致OTP失效。为了解决这个问题,从多个方面进行了方案设计,包括硼磷硅玻璃(BPSG)中硼(B)和磷(P)的浓度,BPSG的厚度,回流温度以及在BPSG之前先沉积一层高密度等离子体氧化物(HDP USG)。实验结果表明,只有在BPSG之前先沉积一层HDP USG的工艺方案才是有效的,才可以消除空洞,从而消除TiN残留物。同时,器件性能不受影响,并实现了高良率。
The process challenge from the 0.18μm based One Time Program(OTP)technology was discussed in this paper.Due to the much more tightened design rule of OTP cell compared to the 0.18μm platform,it is very difficult to fill the gap with a high aspect ratio.As a result,voids across the Contact(CT)were created during the gap filling of the OTP cell.Consequently,at the growth of the TiN glue layer of CTs,it could also grow on the walls of the voids due to the nature of chemical vapor deposition(CVD).TheTiN residues on the void walls will bridge the neighboring CTs,causing the failure of the OTP.To address this process issue,several schemes,including the concentration of Boron(B)and Phosphorus(P)in BPSG,the thickness of BPSG,the reflow temperature of BPSG,and as well as an additional high density plasma undoped Si glass(HDP USG)incorporation before BPSG deposition,were proposed.The results show that the scheme of HDP USG incorporation before BPSG deposition works and is thus employed for the process conditions of mass production.This scheme also shows no impact on electrical properties and can achieve high Chip Probing(CP)yield.
作者
黄庆丰
HUANG Qingfeng(Shanghai Huahong Grace Semiconductor Manufacturing Corporation,Shanghai 201203,China)
出处
《集成电路应用》
2019年第5期30-32,共3页
Application of IC
基金
上海市经济和信息化委员会软件和集成电路产业发展专项基金(1500223)