6.5 kV,5 A 4H-SiC 功率 DMOSFET器件

6.5 kV, 5 A 4H-SiC Power DMOSFET

报道了在60μm厚、掺杂浓度1.3×10^(15) cm^(-3)的外延层上制备4H-SiC功率DMOSFET器件的研究结果。器件击穿电压大于6.5 kV,导通电流大于5 A,相对于之前的报道结果,器件导通能力提升了25倍。器件采用由55根环组成的,450μm宽的浮空场限环作为器件终端结构。通过1 250°C热氧化工艺和NO退火技术,完成器件栅介质层制备。通过横向MOSFET测试图形,提取器件峰值有效沟道迁移率为23 cm^2/(V·s)。器件有源区面积为0.09 cm^2,在栅极电压20 V、室温下,器件比导通电阻为50 mΩ·cm^2。在漏极电压6.5 kV时,器件漏电流为6.0μA,对应器件漏电流密度为30μA·cm^(-2)。基于此设计结构,通过设计实验,提取了SiC DMOSFET器件中电阻比例组成。

The research results of 4 H-SiC power DMOSFETs fabricated by using 60-μm-thick, 1.3×1015 cm-3 doped drift epilayer were reported. The breakdown voltage of the device is higher than 6.5 kV and the on-state current is scaled up to 5 A, which is a factor of 25 increase in device area compared to the previously reported value. A floating guard ring based edge termination structure was used with 55 rings of 450 μm long. The gate oxide layer was formed by thermal oxidation at 1 250°C, followed by an NO anneal. A peak effective channel mobility of 23 cm^2/(V·s) was extracted from a horizontal test MOSFET. A 4 H-SiC DMOSFET with an active area of 0.09 cm^2 showes a specific on-resistance of 50 mΩ·cm^2 at room temperature with a gate bias of 20 V. The device shows a leakage current of 6.0 μA, which corresponds to a leakage current density of 30 μA·cm^2 at a drain bias of 6.5 kV. Base on this design structure, a design-of-experiments has been carried out to extract the resistance components of the SiC DMOSFET.