摘要
本设计采用Verilog_HDL语言设计实现UART系统。该系统由波特率时钟生成模块、数据发送模块和数据接收模块等三个模块组成。经Modelsim模拟仿真显示,各模块设计均满足要求,数据传输速率高、数据传输准确。
This design uses Verilog_HDL language to achieve UART system. The system consists of three modules: the baud rate clock generation module, data sending module and data receiving module. Modelsim simulation shows that the design of each module complies with the requirements, with high data transmission rate and accurate data transmission.
作者
罗春梅
肖顺文
王涌
LUO Chun-Mei;XIAO Shun-Wen;WANG Yong(School of Electronic and Information Engineering,China West Normal University,Nanchong Sichuan 637009)
出处
《数字技术与应用》
2019年第3期150-151,共2页
Digital Technology & Application
基金
四川省教育厅科研基金重点项目(15ZA0145)
