TDI线列型读出电路建立时间问题研究

Research of setup time of TDI line-array ROIC circuits

大规模TDI线列型读出电路在测试中普遍发现建立时间不足,并且,测试结果和仿真结果存在较大差异。读出电路在设计仿真时已充分考虑了电路内部压降、线上阻容寄生的影响以及其他负载效应,但是,在测试中发现,实际电路建立时间是仿真建立时间的2倍,甚至更长。理论上,在应用频率不高的情况下,仿真结果和测试不会出现太大误差。本文针对这一现象,通过大量实验和仿真验证,最终确定线列电路输出级布局布线是造成该问题的关键点所在,通过优化版图提高TDI线列型读出电路的建立时间至1.38 V/30 ns。

In the test of large-scale TDI line-array readout circuit,it is generally found that the set-up time is insufficient,and there is a big difference between the test result and the simulation result.The readout circuit has fully considered the influence of the IR drop,the parasitic and other loads effects in the design and simulation.However,in the test,it is found that the actual circuit set-up time is twice as long as the simulation set-up time,or even longer.Theoretically,the simulation results and the test results will not be much different in the case of low application frequency.In view of this phenomenon,through a large number of experiments and simulation verification,the paper finally determined that the place and route of circuit′s output block cause the problem.By optimizing the layout,the set-up time of TDI line-array readout circuit can be improved to 1.38 V/30 ns.