排序算法的EDA实验设计

The EDA Experiment of Sorting Algorithm

针对速度、资源等不同的应用需求,开发排序算法的最优化硬件实现方案,是数字集成电路设计工作中的重点和难点。该文分别介绍基于面积最优化和速度最优化的硬件实现方法,在此基础上提出一种面积和速度协同优化的设计方案,为排序算法的最优化硬件实现提供参考。同时将排序算法的最优化硬件实现思想融入教学实验中,加深学生对理论的理解和应用,提高学生的设计能力和动手能力。实践表明,该设计方案加深了学生对课堂知识的理解,拓展了课堂所学知识,具有较强的指导意义。

Exploring the optimum sorting algorithm for different application(such as high speed, hardware limitation and so on)is the key and difficult point in design of digital integrated circuits. This paper firstly introduced the hardware implementation method based on area optimization and speed optimization. On this basis,a design scheme of area and speed collaborative optimization is proposed to provide reference for the optimal hardware implementation of the sorting algorithm. At the same time, the optimization hardware realization idea of the sorting algorithm is integrated into the teaching experiment, deepen the students’ understanding and application of the theory, and improve the students’ design ability and hand-on ability. Practice shows that the design program has deepened the students’ understanding of classroom knowledge, expanded the knowledge of the classroom, and has a strong guiding significance.