摘要
In this work, the effects of atomic-layer-deposited(ALD) Al2O3 passivation layers with different thicknesses on the interface chemistry and electrical properties of sputtering-derived HfYO gate dielectrics on Si substrates have been investigated. The results of electrical measurements and X-ray photoelectron sepectroscopy(XPS) showed that 1-nm-thick Al2O3 passivation layer is optimized to obtain excellent electrical and interfacial properties for HfYO/Si gate stack. Then, the metal-oxide-semiconductor capacitors with HfYO/1-nm Al2O3/Si/Al gate stack were fabricated and annealed at different temperatures in forming gas(95% N2+5% H2). Capacitance-voltage(C-V) and current density-voltage(J-V) characteristics showed that the 250℃-annealed HYO high-k gate dielectric thin film demonstrated the lowest border trapped oxide charge density(-3.3 × 1010 cm-2), smallest gate-leakage current(2.45 × 10-6 A/cm2 at 2 V)compared with other samples. Moreover, the annealing temperature dependent leakage current conduction mechanism for Al/HfYO/Al2O3/Si/Al MOS capacitor has been investigated systematically. Detailed electrical measurements reveal that Poole-Frenkle emission is the main dominant emission in the region of low and medium electric fields while direct tunneling is dominant conduction mechanism at high electric fields.
In this work, the effects of atomic-layer-deposited（ALD） Al2O3 passivation layers with different thicknesses on the interface chemistry and electrical properties of sputtering-derived HfYO gate dielectrics on Si substrates have been investigated. The results of electrical measurements and X-ray photoelectron sepectroscopy（XPS） showed that 1-nm-thick Al2O3 passivation layer is optimized to obtain excellent electrical and interfacial properties for HfYO/Si gate stack. Then, the metal-oxide-semiconductor capacitors with HfYO/1-nm Al2O3/Si/Al gate stack were fabricated and annealed at different temperatures in forming gas（95% N2+5% H2）. Capacitance-voltage（C-V） and current density-voltage（J-V） characteristics showed that the 250℃-annealed HYO high-k gate dielectric thin film demonstrated the lowest border trapped oxide charge density(-3.3 × 1010 cm-2), smallest gate-leakage current(2.45 × 10-6 A/cm2 at 2 V)compared with other samples. Moreover, the annealing temperature dependent leakage current conduction mechanism for Al/HfYO/Al2O3/Si/Al MOS capacitor has been investigated systematically. Detailed electrical measurements reveal that Poole-Frenkle emission is the main dominant emission in the region of low and medium electric fields while direct tunneling is dominant conduction mechanism at high electric fields.
基金
financially supported by the National Natural Science Foundation of China (Nos. 11774001 and 51572002)
the Open Fund for Discipline Construction, Institute of Physical Science and Information Technology, Anhui University (S01003101)
<GS3>Top talents in disciplines (Specialties) of universities in Anhui Province<GS3> (<GN3>gxbjZD2016006<GN3>)
the Technology Foundation for Selected Overseas Chinese Scholar, Ministry of Personnel of China (No. J05015131)
the Anhui Provincial Natural Science Foundation (No. 1608085MA06)
