适合短突发通信的定时同步算法仿真与FPGA实现

Simulation and FPGA Implementation of Timing Synchronization Algorithm for Short Burst Communication

在突发通信系统中,快速、高效地完成定时同步对接收机正确接收有重要意义,针对短突发信号持续时间短、不连续的特点,讨论了一种前馈式内插结合数字滤波平方定时频域的定时同步算法。该算法不需要调整本地采样时钟,通过对当前突发信号的采样点进行插值获得最佳采样时刻的采样值,从而实现突发信号的符号定时同步。通过Matlab仿真,给出了不同信噪比条件下算法能适用的短突发最短符号长度以及算法的性能损失。最后给出了算法的FPGA实现方案。

In the burst communication system,the high-speed and high-efficiency timing synchronization is very important for receiver receiving correctly.In view of such characteristics as short duration and discontinuity,this paper discusses a timing synchronization algorithm with feed-forward interpolation combined with digital filter and square timing in frequency domain.The local sampling clock is not adjusted,and the sampling value of the optimal sampling time is obtained through the interpolation of the input short burst signal,so that the digital bit element synchronization can be realized.Through Matlab simulation,the short burst minimal symbol length and performance loss of the algorithm under different SNR conditions are obtained.The FPGA implementation scheme of the algorithm is given.