基于并行约束延迟LMS的高速FPGA信息采集

A parallel constrained delay LMS algorithm for high-speed FPGA information acquisition

在实际的信号传输过程中,原始信号受噪声的影响,噪声源特性未能在不同的环境中提前预测。传统的滤波器系数在设计的阶段已被固定,不可再根据应用调整。传统数字信号处理器实现的自适应滤波器处理速度低、抗干扰性差,导致FPGA信息采集速度比较慢。为了自动消除系统中的非目标带谐波,自适应滤波器根据随机信号的统计描述和模型来预测信号趋势。同时,为了降低资源消耗,提高运行速度,提出了一个并行约束延迟最小均方算法,采用数据转移的方法实现步长因子的更新,理论分析和实验结果表明,与传统方法相比,该方法对于FPGA的高速信息采集方面具有更大的优越性。

In the process of the actual signal transmission, the original signal is affected by noise, the noise characteristics cannot be predicted in advance in different environment.The traditional filter coefficients have been fixed in the design stage and cannot be adjusted according to the application.The adaptive filter implemented by traditional digital signal processor has low processing speed and poor anti-interference performance, which results in the slow speed of FPGA information acquisition.To automatically eliminate the target zone system harmonic, adaptive filter based on random signals of statistical description and model to predict trends, at the same time, in order to reduce resource consumption and improve the running speed, it puts forward a parallel constrained delay least mean square algorithm, and adopts the method of data transfer implementation step length factor.The theoretical analysis and experimental results show that compared with traditional methods, the method for FPGA has greater advantages in the respect of high-speed data collection.