Mealy型序列检测电路的研究和改进

Research and Improvement of Sequence Detection Circuit with Mealy Machine

通过对传统数字逻辑教材的序列检测器设计的研究,指出工作时的输出波形不合理,具体表现在待检测序列最后一位信号出现但时钟尚未有效时,检测器已输出检测结果,合理波形应该是待检测序列最后一位信号出现并且时钟有效,检测器才输出检测结果。经过对设计过程的分析和软件仿真,造成该问题的原因是电路采用Mealy型设计方法,输出受输入和触发器的状态控制,输入的变化即刻影响到输出。本文提出一种摩尔型(Moore)的序列检测器设计方法,输出仅受触发器的状态控制,QuartusII软件的仿真和实际的电路测试验证了设计的有效性和输出波形的合理。

Through the research on the design of sequence detector in the traditional digital logic textbook, it is pointed out that the output waveform of the detector is unreasonable, which is shown in the fact that the detector has outputted the detection result when the last bit signal of the sequence to be detected appears but the clock is not yet effective. The reasonable waveform should wait for the last bit signal of the detection sequence to appear and the clock is valid before the detector outputs the detection result. Through the analysis of the design process and software simulation, the reason for this problem is that the circuit adopts Mealy type design method, the output is controlled by the state of input and flip-flop, and the change of input affects the output immediately. Thus this paper proposes a sequence detector by Moore machine, whose output is only dependent on the state of triggers. The simulation of QuartusII software and the practical circuit test verify the effectiveness of the design and the rationality of the output waveform.