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基于SRAM型FPGA的实时容错自修复系统设计方法 被引量:6

SRAM based FPGA system capable of runtime fault tolerance and recovery
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摘要 为提高辐射环境中电子系统的可靠性,提出了一种基于SRAM型FPGA的实时容错自修复系统结构和设计方法。该设计方法采用粗粒度三模冗余结构和细粒度三模冗余结构对系统功能模块进行容错设计;将一种细粒度的故障检测单元嵌入到各冗余模块中对各冗余模块进行故障检测;结合动态部分重构技术可在不影响系统正常工作的前提下实现故障模块的在线修复。该设计结构于Xilinx Virtex^■-6FPGA中进行了设计实现,实验结果表明系统故障修复时间和可靠性得到显著提高。 In order to enhance the reliability of electronic system working in radiation environment, a reliability enhanced SRAM based FPGA system with runtime fault recovery is presented in this work. Coarse-grained TMR architecture and fine-grained TMR architecture are proposed to achieve the ability of fault tolerance. Fine-grained fault detection units are inserted in each redundancy module to mask the faulty module. The technique of partial dynamic reconfiguration is used to repair the faulty module without interrupting other parts of the system.The scheme is implemented in Xilinx Virtex^■-6 FPGA, and the results show that the improvements in recovery time and reliability are achieved by the proposed technique.
作者 徐伟杰 谢永乐 彭礼彪 沈北辰 Xu Weijie;Xie Yongle;Peng Libiao;Shen Beichen(School of Information Engineering,Chang′an University,Xi′an 710064,China;School of Automation Engineering,University of Electronic Science and Technology of China,Chengdu 611731,China;College of Software Engineering,Sichuan University,Chengdu 610207,China)
出处 《电子技术应用》 2019年第7期50-55,共6页 Application of Electronic Technique
基金 国家自然科学基金(61371049) 长安大学创新实践能力提升子计划项目(300102248806)
关键词 可靠性 故障容错 故障自修复 三模冗余 动态重构 reliability fault tolerance fault recovery TMR dynamic reconfiguration
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  • 1孔德岐,李亚晖,郭鹏.高可靠嵌入式计算机系统的发展[J].通信学报,2013,34(S1):170-175. 被引量:9
  • 2王友仁,姚睿,朱开阳,黄三傲.仿生硬件理论与技术的研究现状与发展趋势分析[J].中国科学基金,2004,18(5):273-277. 被引量:11
  • 3杜文志.航天器FPGA在系统局部重构容错设计研究[J].中国空间科学技术,2005,25(5):10-16. 被引量:9
  • 4陈雪芹,张迎春,耿云海,李化义.基于IMM/EA的卫星姿态控制系统重构容错控制[J].系统工程与电子技术,2007,29(5):774-777. 被引量:6
  • 5Vladimirova T, Wu X F. On-board partial run-time re, configuration for pico-satellite constellations[A]. Prec. of the 1st Conference on Adaptive Hardware and Systems ( AHS' 2006 ) [C]. Istanbal, Turke, 2006. 262 - 269.
  • 6Femanda Lima, Luigi Carro, Ricardo Reis. Designing fault tolerant systems Into SRAM2 based FPGAs[A].40th Design Automation Conference[C]. Anaheim, CA, 2(102.650 - 655.
  • 7Yao X,Hugichi T. Promises and callenges of evolvable hardware[J]. IEEE Trans on Systems Man and Cybernetics-Part C: Applications and Reviews, 1999,29( 1 ) :87 - 97.
  • 8James M H. Fault-tolerant sensor systems using evolvable hardware[J]. IEEE transactions on instrumentation and measurement, 2006,55 (3) : 846 - 853.
  • 9Gregory V L, Jason D L. Evolutionary based techniques for fault tolerant field programmable gate arrays[A]. Proc. of 2nd IEEE International Conference on Space Mission Challenges for Information Technology [C]. Pasadena, California, USA: IEEE, 2006.553 - 560.
  • 10[1]Bedingfield K,Leach R and Alexander M.Spacecraft System Failures and Anomalies Attributed to the Natural Space Environment.NASA Reference Publication-1390,August 1996

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