一种低延迟的3维高效视频编码中深度建模模式编码器

A Low-latency Depth Modelling Mode-1 Encoder in 3D-high Efficiency Video Coding Standard

为了更好地对3D视频中深度图进行编码,该文将3维高效视频编码(3D-HEVC)标准新引入了深度建模模式(DMMs),新模式在提高了编码质量的同时改进了原有算法的复杂度。在设计DMM-1编码器电路时,传统架构电路的编码周期均较长,只能满足较低分辨率和帧率的视频实时编码要求。为了进一步提高3D-HEVC中DMM-1编码器的性能,该文对DMM-1算法架构进行了研究,针对其中楔形块评估无数据相关性的特点,提出了一种5级流水线架构的DMM-1编码器硬件电路,以期能够降低一个深度块编码所需的编码周期,并使用VerilogHDL进行实现。实验表明:该架构与Sanchez等人(2017年)的工作相比,以电路门数增加约1568门为代价,可减少至少52.3%的编码周期。

In order to encode better the depth maps in 3D video,the 3D-High Efficiency Video Coding (3DHEVC) standard is introduced in Depth Modeling Modes(DMMs),which increase the quality of original algorithm while improving the encoding complexity.The traditional architecture of DMM-1 encoder circuit has a longer coding period and can only meet real-time coding requirements of lower resolution and frame rate.In order to improve the performance of DMM-1 encoder,the structure of DMM-1 algorithm is researched and a five-stage pipeline architecture of DMM-1 encoder is proposed.The pipeline architecture can reduce the coding cycles.The architecture is implemented by Verilog HDL.Experiments show that this architecture can reduce the coding cycle by at least 52.3%,at the cost of 1568 gates compared to previous work by Sanchez G.et al.(2017).