基于FPGA的卷积神经网络加速器设计与实现

Design and Implementation of Convolutional Neural Network Accelerator Based on FPGA

卷积神经网络作为传统神经网络的改进,已经获得了广泛的应用。但其实现方式多以软件形式在PC机上运行,在实时性、低功耗和小型化方面都难易适应嵌入式应用需要。鉴于此,本文充分利用现场可编程门阵列(FPGA)的并行计算能力和低功耗等优势,设计了一种基于FPGA的卷积神经网络加速器。采用硬件电路实现方式,充分利用FPGA内部逻辑资源,引入多级流水线并行处理技术,不仅提高运算速度、降低功耗,而且更加适用于嵌入式应用需要。

Convolutional neural network, as an improvement of traditional neural network, has been widely used. However, most of its implementation is in the form of software running on PC, which is difficult to meet the needs of embedded applications in terms of real-time, low power consumption and miniaturization. In view of this, a convolutional neural network accelerator based on field programmable gate array (FPGA) is designed in this paper, which takes full advantage of the parallel computing ability and low power consumption of FPGA. by hardware circuit implementation, making full use of internal logic resources of FPGA and introducing multi-level pipeline parallel processing technology and structured design, the system not only improves the operation speed, reduces power consumption, but also is more suitable for embedded applications.