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面向低抖动GPU像素Cache的像素写合并缓冲技术

Pixel write combining buffer technology for pixel cache low thrash of GPU
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摘要 图形处理器像素Cache访问时抖动发生频繁,很大程度的影响了图形处理器的性能.通过研究图形处理器中多数据流处理的并行化特征,提出了一种像素写合并缓冲技术,在数据写入像素Cache前,根据地址对像素进行合并后再对Cache进行访问,能够减少对Cache的访问次数,降低Cache抖动,提高Cache性能.使用写合并缓冲技术能将Cache抖动平均降低60%,最大降低70%,测试表明像素Cache的写合并缓冲技术能够降低Cache的抖动,非常适用于嵌入式图形处理器像素Cache的设计. The thrashing of pixel cache in GPU is frequent,which greatly decrease the performance of GPU.Based on the research of the parallelization characteristics of multi data stream processing in GPU,apixel write merging buffer technique is proposed.The cache access is merged according to the address before.It can reduce the number of cache access,reduce the cache thrashing,and improve the performance of the cache.The pixel write combining buffer technology can reduce the average cache trash by 60%and the maximum reduction of 70%.The result shows that the write merge buffer technology of pixel cache can reduce the cache thrash,and is very suitable for the design of the pixel cache of the embedded graphic processor.
作者 张淑 田泽 郑新建 张骏 许宏杰 王维 ZHANG Shu;TIAN Ze;ZHENG Xin-jian;ZHANG Jun;XU Hong-jie;WANG Wei(Xi′an Xiangteng Microelectronics Technology Company Limited,Xi’an 710068,China;Aeronautics computing technique research institute,Aviation industry corporation of China,Xi an 710068, China;Key Laboratory of Aviation Science and Technology on Integrated Circuit and Micro-System Design, Xi'an 710068,China)
出处 《微电子学与计算机》 北大核心 2019年第7期93-97,共5页 Microelectronics & Computer
基金 十三五预研项目(31513010202) 核高基重大专项(2016ZX01012101-004)
关键词 Cache抖动 像素缓冲 数据合并 图形处理器 Cache thrash pixel buffer data merge GPU
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