一款10位逐次逼近型模数转换器设计

A 10-bit Successive Approximation Analog-to-Digital Converter

基于0.18μm CMOS工艺设计一款10位逐次逼近型模数转换器(SARADC),采用了阻容混合型的数模转换器(DAC)以实现面积与性能上的折衷,高位采用温度码设计以提高DAC的线性度。采用了失调电压较小的静态比较器结构,通过在DAC和比较器之间加入了高增益的前置放大器来消除比较器失调电压对ADC性能所带来的影响。仿真结果表明:在电源电压为2.8V、采样速率为116kS/s、输入信号频率约为57kHz、满摆幅为0.8V的情况下,ADC有效位数(ENOB)达9.99位,信噪失真比(SNDR)为61.9dB,无杂散动态范围(SFDR)为75.57dB,总功耗约为1mW,面积为0.069mm^2。

A 10 bit successive approximation analog-to-digital converter (SAR ADC) based on a 0.18 μm CMOS process is presented. The proposed SAR ADC employs a RC-capable digital-to-analog converter (DAC) to achieve the trade-off between area and performance, and the high bits of the DAC employ temperature codes to improve the linearity of the DAC. A static comparator structure with small offset voltage is used in the ADC, and a high-gain pre-amplifier is added between the DAC and the comparator to eliminate the effects caused by comparator offset voltage on the ADC performance. The simulation results show that the effective number of bits (ENOB) of the ADC is 9.99 bits and the signal-to-noise ratio (SNDR) is 61.9 dB when the power supply voltage is 2.8 V, the sampling rate is 116 kS/s, the input signal frequency is about 57 kHz, and the swing is 0.8 V. Spurious-free dynamic range (SFDR) is 75.57 dB, the total power consumption is approximately 1 mW, and the area is 0.069 mm^2.