一种280 mW,78 dB SNR,88 dB SFDR流水线ADC设计

Design of a 280 mW, 78 dB SNR, 88 dB SFDR Pipelined ADC

为满足接收机系统的应用需求,采用标准0.18μm CMOS工艺设计实现了一款16bit高精度高速pipelined ADC,电源电压1.8V,采样频率120MHz。为了降低SHA-less结构带来的非线性问题,引入高线性输入缓冲器。测试结果表明,在不明显增加芯片功耗的同时能够实现较高的性能,有效位数达到13bit。输入信号57MHz,幅度-1dBFS时,SNR、SNDR、SFDR分别达到78dBFS、78dBFS、88dB;输入信号313MHz、幅度-1dBFS时,SNR、SNDR、SFDR分别达到70dBFS、70dBFS、78dB。

In order to meet the application requirements of receiver, a 16-bit high-precision and high-speed pipelined ADC with 1.8 V power supply voltage and 120 MHz sampling frequency was designed and implemented using a standard 0.18 μm CMOS process. In order to decrease the nonlinearity caused by the SHA-less structure, a high-linearity input buffer circuit was introduced. The measurement results show that high performance can be achieved without increasing the power consumption of the chip significantly, and effective bits reach 13 bits. When the input signal is 57 MHz and the amplitude is-1 dBFS, the SNR, SNDR and SFDR reach 78 dBFS, 78 dBFS and 88 dB, respectively. When the input signal is 313 MHz and the amplitude is-1 dBFS, the SNR, SNDR and SFDR reach 70 dBFS, 70 dBFS and 78 dB, respectively.