适用于器件并联型ANPC拓扑的低感叠层母排设计方法

Design Method of Low-inductance Laminated Busbar for Device-parallel ANPC Circuit

在高压大容量电力电子设备中,采用叠层母排作为主要连接器件能够降低换流回路杂散电感,减小开关瞬态过程中的电压尖峰,因此叠层母排的设计对高压大容量电力电子装置的性能有着显著影响。为此,针对器件并联型有源中点钳位型(ANPC)拓扑,从换流回路杂散电感大小和不同换流回路杂散电感对称性的角度出发,对比了不同母排层数和空间结构对换流回路杂散电感的影响,给出了一种功率器件对称分布的四层母排设计方法。通过换流回路杂散电感双脉冲实验提取结果,验证了所提出母排结构各换流回路杂散电感理论分析的正确性和仿真计算的准确性。该设计方法能够有效降低器件并联型ANPC拓扑叠层母排换流回路的杂散电感,并使各换流回路杂散电感具有对称性,降低了功率器件的电气应力,提高了各功率器件电气应力的均衡性,有效提高变换器运行的可靠性。

In high-voltage and large-capacity power electronic equipment, using laminated busbar as the main connecting device can reduce the stray inductance of the commutating loops and reduce the voltage spike during the switching transient. Therefore, the design of laminated busbar plays an important role in improving the performance of high-voltage and large-capacity power electronic equipment. Based on the topology of device-parallel active neutral-point-clamped(ANPC) circuit, according to the quantity and the symmetry of the stray inductance of different commutating loops, the effect of different busbar layers and spatial structures on the stray inductance of the commutating loops is compared, and then a four-layer busbar design method with symmetric distribution of power device is proposed. According to double-pulse experiment result for extracting stray inductance, the validity of the stray inductance analysis and accuracy of simulation calculation of each commutating loops of the proposed busbar structure is verified. The design method can be used to effectively reduce the stray inductance of the laminated busbar of device-parallel ANPC circuit and make the stray inductance of each commutating loops symmetrical, which reduces the electrical stress and improves the balance of electrical stress between power devices and improves the reliability of the converter operation effectively.