三维集成电路中内存的经时击穿分析与检测

Analysis and detection of TDDB degradation for DRAM in 3D-ICs

三维多处理器内存堆叠系统能够显著提升系统性能,但伴随而来的热密度以及散热成为影响电路可靠性的关键问题.为了研究并检测三维集成电路结构中内存的经时击穿效应,笔者采用了一种SPICE物理模型,基于蒙特卡罗仿真的方法,对栅极击穿漏电流造成的电路影响进行了分析.同时根据内存中灵敏放大器的特点,笔者提出了基于45nm工艺节点的经时击穿检测电路,适用于大规模存储电路集成;并对检测电路在偏置温度不稳定性影响下的工作情况加以分析.实验仿真结果表明,相比字线驱动电路,灵敏放大器更易受到经时击穿的影响.提出的检测电路可以实现对经时击穿的预警功能并完全覆盖灵敏放大器中由击穿诱发的激活出错问题,且对偏置温度不稳定性效应有良好的鲁棒性.

3D multicore systems with stacked DRAM are capable of boosting system performance significantly,but accompanied with the key problem of the effect of heat density and heat dissipation on circuit reliability.Aiming to study the TDDB (Time Dependent Dielectric Breakdown) effect in DRAM of 3D-ICs,we adopt a physical-based SPICE model and analyze the statistical TDDB degradation induced by the gate leakage current in peripheral circuits of DRAM.Meanwhile,a TDDB detection design is proposed based on the 45nm process,which is suitable for large scale integration of the memory circuit.And the operation of the detection circuit is analyzed based on the BTI (Bias Temperature Instability) effect.Experimental results show that sense amplifiers are more susceptible to time dependent dielectric breakdown than word-line drivers in DRAM.The proposed TDDB detection design can completely meet the maximum fault coverage rate with good robustness to BTI,and it will send out an alarm signal when TDDB happens in the sense amplifier.