一种基于ADF4360-9和FPGA的合成时钟源设计

A synthetic clock source design based on ADF4360-9 and FPGA

为了获得稳定可靠的时钟源,设计了一种合成时钟源。通过FPGA产生控制信号,结合硬件电路和软件设计,控制ADF4360-9时钟芯片输出,得到稳定的时钟模块。ModelSim软件测试结果表明了程序时序的正确性,且实际测试的相位噪声与仿真的相位噪声基本一致,本时钟源相位噪声理想,稳定可靠。

In order to obtain a stable and reliable clock source,a synthetic clock source is designed.That is,the control signal is generated by the FPGA,combined with the hardware circuit and software design,the output of the ADF4360-9 clock chip is controlled,and a stable clock module is obtained.The ModelSim software test results show the correctness of the program timing,and the phase noise of the actual test is basically consistent with the phase noise of the simulation,indicating that the phase noise of the clock source is ideal,stable and reliable.