人体心电信号数字处理及控制模块的SOPC设计

Sopc Design of Digital Processing and Control Module for Human ECG Signal

用FPGA“片上系统”结构取代目前心电监护仪所采用的DSP和MCU或ARM微处理器双CPU结构,构建ECG信号处理模块,实现对ECG信号的数字处理和控制。模块设计采用软硬件协同设计的思想,在QuartusⅡ开发环境中,通过硬件描述语言(VHDL)或采用SOPC定制IP核技术完成AD控制器、心率处理器、FIR滤波器以及寄存器编码等子模块的设计,实现相关逻辑功能。该模块研制周期短,成本低,精度高、体积小、功耗低,具有较好的实用性和可扩展性,特别适应可穿戴设备和移动医疗的需要。

The structure of FPGA ‘on-chip system’ is used to replace the DSP and MCU or ARM microprocessor dual CPU structure which used in the current ECG monitor, and the ECG signal processing module is constructed to realize digital processing and control of the ECG signal. The module is designed with the idea of hardware and software co-design. In the QuartusⅡ development environment, the design of sub-modules such as AD controller, heart rate processor, FIR filter and register code is completed by hardware description language(VHDL) or custom SOPC IP core technology to achieve the related logic functions. The advantages of module is that has short development cycle, low cost, high precision, small size, low power consumption, good practicability and scalability, and it is particularly suitable for wearable devices and mobile medical.