90 nm CMOS工艺平台金属硅化物工艺优化及其表征

Silicide Formation Process Optimization and Characterization on 90 nm CMOS Technology Platform

半导体制程发展到0.18μm节点及以下时,主要采用金属钴硅化物来降低扩散区的电阻和接触孔的接触电阻。当工艺节点缩小到90nm时,由于结深变浅,金属钴硅化物的厚度和均一性对结漏电的影响越来越显著。针对金属钴硅化物形成的多个工艺参数进行调整,并通过电特性参数中不同尺寸扩散区及栅极电阻的变化以及透射电镜图像来表征。

In standard CMOS manufacture technology, silicide is used to decrease the resistance of both active and contact resistance.Cobalt silicide is adopted on 0.18 μm technology node and below. When it comes to 90 nm technology node, due to the shallower junction depth, the impact of cobalt silicide thickness and uniformity on junction leakage becomes more and more significant. Several silicide formation process parameters have been altered and characterized by different size active and poly resistance and TEM photos.