功率VDMOS器件抗SEGR的仿真研究

Simulation Research on Resistant SEGR of Power VDMOS Devices

针对功率垂直双扩散金属氧化物半导体场效应晶体管(VDMOS)器件单粒子辐射在空间辐射环境下的要求,从重粒子对VDMOS器件的辐射机理及作用过程出发,通过对200 V抗辐射VDMOS器件进行大量仿真研究发现,器件的元胞间距对VDMOS的抗单粒子栅穿(SEGR)能力有很大的影响,由分析结果可以看出,当元胞间距减小为1 jxm时对于栅氧层表面电场的改善最为明显,但是导通压降会明显提高。为了在提高抗SEGR能力的同时,使器件的导通压降值适当,在两个元胞之间加入了结型场效应晶体管(JFET)电荷泄放区结构,在保证器件的基本特性的同时,抗SEGR能力也得到明显改善。

The failure mechanism and action process of vertical double-diffused metal oxide semiconductor (VDMOS) radiated by heavy ions are analyzed for performing some hardened technologies on power VDMOS used in space environment. Through extensive simulation research on 200 V radiation -resistant VDMOS devices, it is found that the cell spacing of the device has a great influence on the single event gate-rupture (SEGR) resistance of VDMOS.lt can be seen from the analysis results that when the cell spacing is reduced to 1 Jim, the improvement of the electric field is most obvious, but the on-resistance will increase significantly.In order to improve the SEGR while the device's turnon voltage drop is appropriate, a junction field-effect transistor(JFET) structure is added between the two cells.The SEGR capability is also significantly improved while ensuring the basic characteristics of the device.