一种10 bit 50 MSps分段式电流舵DAC设计

Design of A 10 Bit 50 MSps Segmented Current-steering DAC

本文基于40 nm CMOS工艺,设计了一种10 bit 50 MSps的DAC,该DAC内嵌于一款4 GSps 12 bit的ADC核内进行非线性校准的工作.DAC电路的主体为分段式结构,高6位和低4位分别为温度计码和二进制码.本文提出一种利用模拟电路来进行二进制码转温度计码的设计,可以有效的提高DAC的INL及减小译码电路版图的面积.为了减小因版图布局而引起的失配误差,电流源阵列采用Q2 Random Walk布局.版图后仿的结果显示,在1.8V电源供电下,DAC的DNL和INL的最大绝对值分别为0.04 LSB和0.015 LSB.当仿真时的输出信号频率为0.098 MHz时,DAC的SFDR为73.5 dB.

Based on 40 nm CMOS process,a 10 bit 50 MS/s DAC is designed for nonlinear calibration of a 4 GSps 12 bit ADC core. A segmented current steering architecture is designed as the main structure of this DAC circuit,in which the upper 6 bits and the lower 4 bits are the thermometer codes and the binary codes,respectively. For effectively improving the INL of the DAC and scaling the layout of the decoder circuit,an analog circuit dedicated to converting the two is designed into the main architecture. In order to reduce the mismatch error from layout,the current source array adopts the Q2 Random Walk switching scheme. The simulation result after extracting the layout’s parasitic parameters shows that the maximum absolute value of the DNL and INL of DAC are 0. 05 LSB and 0. 026 3 LSB,respectively,at a 1. 8 V supply voltage. When the frequency of the output signal selected by the simulation is 0. 098 MHz,the SFDR of the DAC is 74 dB.