基于SPCB的处理器直连低延时PCS的设计实现

Design and implementation of SPCB-based processor directly connected low delay PCS

SERDES(串行解串)技术因其传输速率高、抗干扰能力强等优点已成为主流的高速接口物理层规范。但由于上层PCS(物理编码子层)需设置弹性缓冲、编解码等功能,导致系统传输延时较高,无法直接应用于处理器直连等延迟敏感应用领域。介绍了一种基于同源相位补偿缓冲(Synchronous Phase Compensation Buffer,SPCB)的PCS架构的设计实现,可应用于延时敏感的SERDES接口传输系统。该架构具有高吞吐率和超低延时的特点,通过定制的SPCB,单通道32Gb/s时,发送与接收通路传输延时为10ns左右,约为业界典型PCS方案的一半,达到Intel与AMD并行CPU直连接口(QPI和HT)的延时水平。该PCS架构可通过28nm/16nm/7nm工艺物理实现,已应用于多款国产处理器直连接口。

SERDES(serial de-serialization) technology has become the mainstream physical layer specification of high-speed interface due to its high transmission rate and strong capacity of resisting disturbance.However,the upper PCS(physical coding sublayer) needs to set elastic buffering,code,encode and do other functions,so the system transmission delay is high.SERDES cannot be directly applied to delay sensitive applications such as processor direct connection.This paper introduces a design of PCS architecture based on synchronous phase compensation buffer(SPCB),which can be applied to delay sensitive SERDES transmission system.This architecture features high throughput and ultra-low latency.With a custom SPCB,the transmission reception path delay is about 10 ns at 32 Gb/s per lane,which is about half of the typical PCS delay in the industry,reaching the level of Intel(QPI) and AMD(HT) interface.This PCS architecture can be realized through 28 nm/16 nm/7 nm chip manufacturing tech,and has been applied to a variety of domestic processor.