一种整数分频电路及高性能数据通路实现方法

针对数字电路设计中高性能数据通路设计实现的广泛需求,基于再生逻辑块以实现提高的吞吐量[1]的设计实现方法,提出一种该方法所需的整数分频/使能信号的电路和设计实现。相对于传统分频电路中设计繁琐,占用片上资源较多等缺点,提出的电路和设计方法具有设计简单,易于实现,节约设计资源,节省功耗,并且具备可根据再生(复用)逻辑块的配置动态调节分频信号或者使能信号的分频比和占空比的特点。

To implement high performance datapath, based on replicated logic blocks to increase the throughput of the pipeline design method, an integer clock(frequency) divider/enable signal generator is proposed to generate the required signals for each logic blocks. Compared with the traditional integer frequency divider, the proposed design is simple, easy to implement, low in gate count as well as capable of reducing power consumption. The division ratio and duty cycle of the output clock/enable signal can also be adjusted on-the-fly according to the different configuration of replicated logic blocks.