一种基于相变存储器的高速读出电路设计

A High-Speed Read Circuit for Phase-Change Random-Access Memory

通过对相变存储器中的读出电路进行改进,以提升存储器的读出速度;通过降低读出电路中灵敏放大器输出端电压摆幅,使得输出端电压提早到达交点,显著减小了读出时间;同时,基于中芯国际集成电路制造有限公司(SMIC)40 nm的互补金属氧化物半导体(CMOS)芯片制造工艺,利用8 Mb相变存储器芯片对改进的新型高速读出电路进行验证,并对新型电路的数据读出正确性进行仿真分析.结果表明:在读Set态相变电阻(执行Set操作后的低电阻)时,新型电路与传统读出电路的读出时间均小于1 ns;在读Reset态相变电阻(执行Reset操作后的高电阻)时,新型电路相比传统读出电路的读出速度提高了35.0%以上.同时,采用蒙特卡洛仿真方法所得Reset态相变电阻的读出结果表明:在最坏的情况下,相比传统读出电路的读出时间(111 ns),新型电路的读出时间仅为58 ns;新型电路在最低Reset态相变电阻(RGST=500 kΩ)时的读出正确率仍可达98.8%.

The read circuit in phase-change random access memory(PCRAM)is improved to effectively accelerate the memory’s read speed.By reducing the output voltage swing of the sense amplifier in read circuit,output voltages can reach the intersection point earlier than before,so that can decrease the read access time.Based on SMIC 40 nm complementary metal oxide semiconductor(CMOS)process,the novel high-speed sense amplifier is verified at an 8 Mb PCRAM chip.The simulation results show that the read speeds of the novel circuit and the conventional circuit both are less than 1 ns when the Ge2Sb2Te5(GST)resistance in set state(low resistance after set operation)is read.And the read speed can be accelerated more than 35.0%in the novel circuit compared to the conventional read circuit when the GST resistance in reset state(high resistance after set operation)is read.Monte Carlo simulation(the GST resistance in reset state)shows a 58 ns worst read access time compared to the conventional circuit 111 ns.And the read correctness of the novel read circuit was simulated in this paper.The simulation results show that the read validity can reach 98.8%in the worst reset resistance case(RGST=500 kΩ).