基于三步旋转坐标旋转数字计算机算法的直接数字频率综合器实现

Implementation of direct digital frequency synthesizer based on three-step rotation coordinate rotation digital computer algorithm

提出基于三步旋转机制的高精度低时延坐标旋转数字计算机(CORDIC)算法.该算法通过对输入角度进行二极化重编码来免除剩余旋转角度的运算,利用三步旋转机制对迭代次数进行压缩,结合合并迭代技术进一步减少迭代次数,降低输出时延.以16位输出位宽为例,对三步旋转CORDIC算法和流水线迭代式算法进行实现,仿真结果表明:三步旋转CORDIC算法与流水线迭代式算法相比,改善了输出精度,输入到输出的时延降低了75%,硬件开销下降了29.2%.基于三步旋转CORDIC算法,实现了相位累加器位宽为24的直接数字频率综合器(DDFS);使用加法树结构对多输入加法器进行优化,以提高电路工作频率.仿真结果表明,该算法的最大幅度误差为8.24×10^-6,输出时延为38.5 ns.

A high precision and low output delay coordinate rotation digital computer(CORDIC) algorithm based on three-step rotation mechanism was proposed. The operation of the residual rotation angle was avoided by binary to bipolar recoding of the input angle, the number of iterations was compressed by three-step rotation mechanism, and the number of iterations and output delay were reduced by combining with merging iteration technique. The threestep rotation CORDIC algorithm and pipeline iterative algorithm were implemented by taking 16-bit output bit-width as an example. The simulation results show that the three-step rotation CORDIC algorithm improves the output accuracy, reduces the input-output delay by 75%, and reduces the hardware overhead by 29.2% compared with the pipeline iterative algorithm. The direct digital frequency synthesizer(DDFS) with a phase accumulator of 24 bits bitwidth was implemented based on the three-step rotation CORDIC algorithm, and the multi-input adder was optimized with the addition tree structure in order to improve the circuit frequency. The simulation results showed that the maximum amplitude error of the algorithm was 8.24 × 10^-6, and the output delay was 38.5 ns.