一种高能效的Keccak算法ASIC设计与实现

Design and implementation of an energy-efficient Keccak algorithm ASIC

设计并实现了能同时支持SHA3四种模式的Keccak算法完整硬件电路。在对海绵结构和Keccak算法详细分析的基础上,将电路结构划分为并行执行的填充模块和置换模块,减少了算法执行的时钟周期。在所设计的Keccak算法硬件电路基础上,从能效角度对三种现有置换函数实现结构进行了比较分析。在65nm工艺库下进行综合,SHA3-256标准下单位面积性能达到0.55Mbps/gate,相较现有结构能效提高了约52%。

The complete hardware circuit of Keccak algorithm which can support the four modes of SHA3 is designed and implemented. Based on the detailed analysis of the sponge functions and Keccak algorithm, the modular idea is used to divide the circuit structure into parallel filling modules and replacement modules, which reduces the clock cycle of task execution. Based on the designed Keccak algorithm hardware circuit as the basic structure, the three existing permutation function implementation structures are compared and analyzed from the aspect of energy efficiency. Integrated under the 65 nm process technology library, the SHA3-256 standard energy efficiency reaches 0. 55 Mbps/gate, which is about 52 % more energy efficient than existing structures.