垂直双栅MOSFET的性能设计和仿真分析

Performance design and simulation analysis of vertical double gate MOSFET(VDGM)

针对纳米器件应用程序,本文设计了两侧绝缘支柱上带有双栅结构的垂直金属氧化物半导体场效应晶体管(MOSFET);考虑掺杂效应对垂直通道长度的影响,并对这些Lg=50nm的小型设备的工作效果进行分析;将Lg为50nm的设备与传统平面MOSFET进行比较,进而分析其性能;最后对创新设计进行评估,在纳米级领域中将结合了电介质容器(DP)的垂直MOSFET转塔与标准垂直MOSFET的设备性能进行全面的分析比较。结果表明优化掺杂效应可使垂直MOSFET的性能得到极大增强。在DP的排放端附近,源极和漏极之间的电荷共享现象减少,提高了势垒区的栅控制效果,抑制了纳米器件结构的短沟道效应(SCE)。

Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length,Lg=50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling Lg down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket(DP)on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect(SCE)suppression in nanodevice structure.