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一种适于Sigma-Delta ADC的高增益放大器的设计 被引量:5

A Design of a High-Gain Amplifier for Sigma-Delta ADC
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摘要 设计了一种应用增益增强技术和斩波稳定技术的全差分折叠式共源共栅运算放大器;整体放大器采用了折叠式共源共栅结构,主运算放大器采用增益增强技术和开关电容共模反馈,两个辅助运算放大器采用连续时间共模反馈以实现高增益;此外,还采用了斩波稳定技术,在放大器的前后加入斩波开关,达到了滤除低频噪声的效果;在基于SMIC 55nm工艺库,电源电压3.3V下,在Cadence平台利用Spectre进行模拟仿真,仿真结果表明:等效输出噪声低频处的噪声被滤除,运算放大器的增益为116.9dB,相位裕度为72°,单位增益带宽为355MHz,能够使放大器应用于低频域,能够满足Sigma-Delta调制器对于音频频域的设计需要。 A fully differential operational-amplifier used in a high gain ADC is designed.This op-amp adopts folded cascade to achieve high gain while the main op-amp uses gain-enhancement technique and switch capacitor common-mode feedback and the two auxiliary op-amps use continuous time common-mode feedback.In addition,it also uses the chopper stabilization,adding the chopper switch to the front and rear structures of the amplifier,so as to achieve the effect of filtering out the low-frequency noise. Based on SMIC 55nm,3.3Vprocess,the simulation results show that the low-frequency noise of output noise is filtered out.the DC-gain of op-amp is 116.9dB,phase margin is 72°and unity-gain bandwidth is 355MHz,that can make the op-amp suitable for low-frequency domain and meet the needs of Sigma-Delta’s modulator design of audio domain.
作者 田海燕 李斌 廖春连 Tian Haiyan;Li Bin;Liao Chunlian(54th Research Institute of China Electronics Technology Group Corporation,Shijiazhuang 050000,China)
出处 《计算机测量与控制》 2019年第10期268-272,共5页 Computer Measurement &Control
关键词 放大器 共源共栅 增益增强 共模反馈 斩波技术 operational-amplifier cascade gain enhancement technique common-mode feedback chopper stabilization
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  • 1苏立,仇玉林.一种全差分增益提升运放的设计与建立特性优化[J].电子器件,2006,29(1):162-165. 被引量:4
  • 2何峥嵘.运算放大器电路的噪声分析和设计[J].微电子学,2006,36(2):148-153. 被引量:50
  • 3LLOYD J,LEE Hae-Seung.A CMOS op amp with fully- differential gain-enhancement[J].IEEE Analog and digital signal processing, 1994,41 (3) : 241-243.
  • 4YUN Chiu,PAUL R.G,NIKOLIC B.A 14 b 12 MS/s CMOS pipeline ADC with over 100 dB SFDR[J].IEEE Journal of Solid- State circuits, 2004,38 (12) : 2139- 2151.
  • 5GERMANO N,PIERANGELO C,DANIEL S.A fully differential sample-and-hold circuit for high-speed applications [J].IEEE Journal of Solid-State Circuits, 1989,24(5): 1461-1465.
  • 6CHOKSI O,RICHARD L C.Analysis of switched-capacitor common-mode feedback circuit[J].IEEE Analog and digital signal processing, 2003,50(12) : 906-917.
  • 7CHOKSI O,RICHARD L C.Analysis of switch-capacitor commom-mode feedback circuit[J].IEEE Transactions on circuits and systems-2:Analog and digital signal processing 2003,50(12) : 906-917.
  • 8AMINZADEH H, DANAIE M, LOTFI R.Design of high- speed two-stage cascade-compensated operational amplifiers based on settling time and open-loop parameters[J].INTE- GRATION ;The VLSI journal 41(2008) : 183-192.
  • 9拉扎维,陈贵灿等编译.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003:75-77,.
  • 10ZHANG S, HUANG Lu, LIN Bei Yuan.Design of a low- power,high speed op-amp for 10 bit 300 Ms/s parallel pipelined ADCs.Proceeding fo the 2007 IEEE International Conference on Integration Technology ,2007:504-507.

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