一种基于共用存储空间的FPGA的QC-LDPC码并行译码架构

A QC-LDPC parallel decoding architecture based on FPGA with shared storage space

针对QC-LDPC码并行译码FPGA实现结构复杂、资源消耗大等不足,文章提出一种中间计算变量的共用FPGA存储资源的QC-LDPC码并行译码架构,此架构通过两个交织单元,使得变量更新节点和校验更新节点的结构使用同一个存储资源,该架构具有控制简单、效率高和存储需求量低等优点,适用于高速卫星、地面等通信系统接收机中。

Aiming at the problem of the complex structure and resource consumption of the QC-LDPC parallel decoding in FPGA,a QCLDPC parallel decoding architecture based on intermediate computing variables witch sharing FPGA storage resources is proposed in this paper.In this architecture,the variable update node structure and the check update node structure share the same storage resource through two interlocking units.This architecture has the advantages of simple control,high efficiency and low storage demand,and is suitable for high-speed satellite,ground and other communication system receivers.