摘要
提出了一种基于翻转电压跟随器(FVF)的无片外电容低压差线性稳压器(LDO)。采用电压检测器来检测输出电压,大幅改善了瞬态响应,克服了常规LDO面积大、需要使用片内大电容的缺点,仅消耗了额外的静态电流。该LDO采用90nm CMOS工艺进行设计与仿真,面积为0.009 6mm^2,输入电压为1.2V,压差为200mV。结果表明,在50pF负载电容、3~100mA负载电流、300ns跃迁时间的条件下,产生的上冲电压为65mV,瞬态恢复时间为1μs,产生下冲电压为89mV,瞬态恢复时间为1.4μs,且将负载调整率性能改善到0.02mV/mA。
A capacitor-less low dropout regulator (LDO)based on Flipped Voltage Follower (FVF)was presented.With an output voltage detector,the proposed LDO greatly improved the load-transient response by monitoring the variation in output voltage in the steady state and consumed only additional quiescent current.The output voltage detector overcame the shortcomings of the direct voltage-spike detection that the LDO occupied a large chip area and needed a big on-chip capacitor.The proposed circuit was fabricated in a 90nm CMOS process and occupied an active chip area of 0.009 6mm2.The circuit’s input voltage was 1.2Vand the dropout voltage was 200 mV.Experimental results showed that the maximum overshoot and undershoot was 65mV and 89mV respectively for 3mA to 100mA load current change within 300ns edge time,and the recovery time was 1μs and 1.4μs respectively when a 50pF on-chip output capacitor was applied.And the load regulation could be improved to 0.02 mV/mA.
作者
王瑄
王卫东
WANG Xuan;WANG Weidong(School of Information and Communication,Guilin University of Electronic Technology,Guilin,Guangxi 541000,P.R.China)
出处
《微电子学》
CAS
北大核心
2019年第5期674-679,共6页
Microelectronics
基金
国家自然科学基金资助项目(61461014)