VHDL-C++翻译器设计与实现

Design and Implementation of a VHDL-C++ Translator

VHDL(VHSIC(very high speed integrated circuit) hardware description language)是描述数字系统的硬件描述语言,C++是编写顺序语句程序的高级编程语言.VHDL编译型模拟器需要采用具有顺序特征的C++语句表征具有并发特征的VHDL电路设计.提出了一种面向对象的VHDL-C++翻译方法,充分利用了这两种语言的面向对象的特征,采用C++类来描述VHDL的实体、结构体及进程等元素,并通过一个C++模拟调度核心完成了用顺序语句描述并发电路的工作.通过此方法可将VHDL源描述转化为功能等价的C++代码,并在模拟调度核心的调度下,使用顺序语句模拟出数字系统并发功能,完成编译型模拟器的构造,实现VHDL的高速模拟.用这种翻译方法翻译出来的C++代码具有结构清晰、可扩充性强的特点,与模拟核心形成的编译型模拟器的模拟速度相比,解释型模拟器速度有较大提高.该方法已在模拟系统中得以成功应用.最后给出了部分试验结果,进一步说明了算法的效率和优点.

VHDL (VHSIC (very high speed integrated circuit) hardware description language) is a language for the description of digital hardware system, and C++ is a programming language for coding sequential statements. VHDL compiled simulators use sequential C++ language to model circuits in VHDL with concurrent characterization. An object-oriented method of translating concurrent VHDL codes into sequential C++ codes is presented in this paper. This method takes the object-oriented characteristic of the two languages into consideration and makes the translation very smooth. Using class of C++ to model entity, architecture and process of VHDL, and combining with a simulation kernel, it accomplishes the job of modeling concurrent actions using sequential statements. By this method, VHDL codes can be translated to C++ codes with the same function, and the C++ codes then can be compiled and linked with simulation kernel code to an executable file, which is the compiled simulator. The execution of this file is the simulation of the design of VHDL. This method is well-structured and easily-extended, and the simulator got by this method is more efficient than the traditional one. This method has been successfully applied in the simulator. The performance and efficiency of the method are verified at the end of of this paper.