摘要
讨论了一种适合于 VL SI的精密定时子系统的新结构 .该结构将定时计数器分为高速和低速两部分 ,低速部分采用存储器代替分散的寄存器 ,既有利于集成 ,又降低了系统的成本 .同时 。
A new structure of accurate clock generate subsystem is presented which is fit for VLSI design.The timing counter is divided into two parts,one for high speed and the other for low speed.Registers in low speed part are replaced by centralized memories,which decrease the wiring complexity and reduce the cost.Programmable counter and peripheral control circuits are designed to solve the problem of timing in incomplete period.The new clock generator can work at 100MHz and the total timing period can be up to more than 1h.
