用于视频压缩的三步法并行硬件实现

A parallel architecture for three-step search

根据三步搜索法的特点 ,研究了运动估计的实现结构 ,提出了一种基于并行结构的三步搜索算法实现方法 .在该方法中采取了数据复用的原则 ,减少了读取存储器数据的次数 ,极大地减少了I/O端口数目 ,使硬件实现变得简单易行 ,且处理速度比传统结构的高一倍 .

Based on the character of the three step search algorithm (3SS), the architecture for motion estimation is studied. A parallel architecture for 3SS is presented, in which the repetitive data are reused. Then the number of times of accessing the SRAM and the number of I/O are greatly reduced. This architecutre is suitable for VLSI implementation with the speed higher than that of the conventional architecture.