三维互连电感电阻的快速提取

A 3-D Fast Inductance and Resistance Extractor for Interconnects

VLSI电路的特征尺寸已降至深亚微米量级 ,频率已达 2GHz .为保证高性能电路设计的正确性 ,需快速而精确地计算互连寄生电感电阻 .本文提出了一种适合三维层次互连结构的描述格式 ,提出一种考虑趋肤效应的电流细丝自动划分方法 ,实现了改进的非均匀立方体划分多极加速计算 .数值结果表明 ,在可比精度下 ,它比当前十分先进的多极加速提取软件FastHenry[1]

With the development of the VLSI circuits,the feature size has been decreased to the deep sub micron level,andworking frequency has reached to 2GHz. In order to assure the correctness of the IC design with high performance,the parasitic interconnect inductance and resistance should be calculated quickly and accurately.In this paper,we propose a description format to fit for 3 D hierarchical interconnect,an approach to automatically partitioning filaments in consideration of skin effect.An improved multipole accelerative computation based on the non uniform cube subdivision is implemented.Numerical results show that it runs faster than the FastHenry from several to several tens' times with comparable accuracy.