VLSI测试中移相伪随机序列的设计

Design of Pseudorandom Sequences with Phase Shifts for VLSI Test

为了用较少的硬件和测试时间开销获得对被测电路较高的故障覆盖,提出了一种数字集成电路测试中多扫描链的配置方法。该方法基于最大周期的线性反馈移位寄存器LFSR生成的m序列的移位可加性,可使较短长度的LFSR驱动多个扫描链;为了减小LFSR生成序列的互相关性,利用LFSR与其对偶LFSR间的关系,提出了基于逻辑仿真的移相器的快速设计方法,实验结果验证了该方法的有效性,对VLSI的内测试和外测试皆适用。

This paper aims at achieving higher fault coverage for circuits under test with less hardware overhead and time consumption. One Configuration approach of multiple scan chain is presented based on the shift-and-add property of m sequence generated by Linear Feedback Shift Register (LFSR) with maxium sequence length, it enables LFSR with shorter size to drive multiple scan chains. In order to alleviate correlation between the bit streams of LFSR, a fast design meathod is presented also based on logic stimulation. Experiment results prove the effectivness of this approach, it can be used both to internal test and external test of VLSI.