用于高速电荷域ADC的电荷比较器设计

Design of the Charge Comparator for High Speed Charge Domain ADC

设计了一种用于电荷域流水线ADC的高速电荷比较器电路,该比较器包括电荷采样电路、共模不敏感开关电容网络和锁存放大器。仿真结果表明,在0.18μm CMOS工艺条件下,该比较器在250 MHz时钟下性能良好,采用该比较器的12位250 MS/s电荷域ADC内的2.5位子级电路功能正确。

The design of a charge comparator for high speed charge domain pipelined ADCs is presented.Charge sampler,common-mode insensitive switched-capacitor network and lacthed amplifier are introduced in the charge comparator.The comparator is used in a 2.5-bit sub-stage circuit for a 12-bit 250-MS/s charge domain pipelined ADC and realized in 0.18μm CMOS technology.Simulation results show that the charge comparator and the 2.5-bit sub-stage circuit can work correctly at the clock rate of 250 MHz.