用于卷积神经网络硬件加速器的3D DMA控制器

在卷积神经网络硬件加速器(Convolutional Neural Networks Accelerator,CNNA)中,需要大量的数据访问和中间数据缓存,系统架构中负责数据传输的DMA控制器(Direct Memory Access Controller,DMAC),性能高低将直接影响整个加速器的算力。针对传统DMAC传输三维图像特征(feature)和权重(weight)时,需多次加载数据到内存的问题,本文创新性的提出了一种专用于CNNA的3D(Width,Height,Channel)DMAC的设计。整个架构有四个DMAC,每个DMAC支持单通道传输,可以并行工作互不影响。设计的DMAC支持多种操作模式,除基本的直接内存访问模式,还包括3D模式,即支持3D图像数据控制,极大提高了加速器的工作效率。本设计已用verilog语言在RTL上建模,并对功能进行了综合、仿真和验证,结果表明设计满足应用需求。

In Convolutional Neural Networks hardware accelerator,a large number of data access and intermediate data caching are needed.The performance of DMA Controller,which is responsible for data transmission,directly affects the computational power of the accelerator.Aiming at the problem of loading data several times when traditional DMAC transmits 3D(Width,Height,Channel)feature and weight into memory,this paper proposes an innovative design of 3D DMAC dedicated to CNNA.The whole architecture has four DMACs.Each DMAC supports single channel transmission and can work without affecting each other.In addition to the basic direct memory access mode,it also includes 3D mode,which supports 3D image data operation,greatly improving the work efficiency of the whole accelerator.The design has been modeled on RTL with Verilog language,and the functions have been synthesized,simulated and verified.The results show that the design meets the requirements.