SRAM冗余存储阵列分析与控制电路设计

SRAM redundant memory array analysis and corresponding control circuit design

SRAM存储阵列设计制造时常使用工艺允许的最小晶体管以提高面积效率,因此极易因工艺参数变化从而导致器件失配。而为提高存储阵列良率,本文提出一种在存储阵列中加入冗余行和冗余列存储单元的方式,并设计相应的冗余存储阵列控制电路。该方式可以通过冗余控制电路控制冗余存储阵列替代有缺陷存储阵列从而完成存储阵列纠错。该电路结构已成功应用于一款双端口异步SRAM存储器中。

SRAM memory arrays are often designed with using the smallest transistors allowed by the process to increase area efficiency,making it extremely easy of device mismatch.In order to improve the yield of the memory array,this paper proposes a way that to add redundant rows and redundant column memory units to the memory array,and design control circuits corresponding redundant units.In this way we can use redundant units to replace defective memory units by the control circuits to recover.This circuit structure has been successfully applied to a dual-port asynchronous SRAM memory and working.