高性能计算机有向指数步长环网拓扑结构设计（英文）

Design of Directed Exponential-step Loop Topologies for HPC Interconnects

针对高性能计算(HPC)系统规模的增大导致的通信延迟和物理电缆长度增加等不利因素,提出一种新的用于高性能计算机互连的有向指数步长环网拓扑结构。仿真结果表明:与随机步长相比,其可以进一步降低30%的通信延迟,同时降低封装复杂性和物理电缆长度;与固定步长和随机步长拓扑在生成拓扑后计算通信延迟不同,该方案能够在生成拓扑之前考虑延迟。文中还就延迟、封装复杂度、物理电缆长度、可扩展性等方面,将指数步长与固定步长和随机步长的拓扑结构进行了比较。

The increase of the scale of high performance computing(HPC)system leads to communication delay and physical cable length increase.Thus,we proposed a novel directed exponential-step loop topology for HPC interconnections.Simulation results show that:compared to the random-step counterpart,it can further reduce the communication latency by up to 30 percent,and meanwhile,reduce packaging complexity and physical cable length;Contrary to fixed-step and random-step topologies that calculate communication latencies after generating the topologies,the proposed scheme is able to estimate the latencies before generating the topologies.Besides,this paper extensively compares the proposed exponential-step with the fixed-step and random-step topologies in terms of delay,packaging complexity and physical cable length,scalability.