一款精准低噪声运算放大器输入级的优化设计

Optimization Design of the Input Stage of a Precise Low Noise Operational Amplifier

基于4μm 40 V互补双极工艺,设计了一款精准、低噪声、轨到轨输入输出运算放大器。电路采用轨到轨互补输入级,并在此基础上采用了一种新型的低噪声偏置电流补偿电路,该结构的电流噪声与运算放大器输入双极晶体管的电流噪声为相关噪声,同时该电路还可大幅降低运算放大器的输入偏置电流,减小源电阻噪声对电路的不良影响,从而确保运算放大器具有极低的等效输入电压噪声和电流噪声。测试结果表明,利用该结构设计的轨到轨输入输出运算放大器,其带宽为5.05 MHz,大信号低频增益为136.2 dB,输入偏置电流仅为29.8 nA,输入失调电流为11.9 nA,输入失调电压为188μV,输入电压噪声密度为■、共模抑制比(CMRR)为121.6 dB,电源抑制比(PSRR)高达117.3 dB。

Based on the 4 μm 40 V complementary bipolar process, a precise, low noise and rail-to-rail input/output operational amplifier was designed. Based on the rail-to-rail complementary input stage, a new kind of low noise bias current compensation circuit was used. The current noise of the proposed structure was correlated with the current noise of the operational amplifier input bipolar junction transistors. At the same time, the circuit can also greatly reduce the input bias current of the operational amplifier and reduce the adverse impact of the source resistance noise on the circuit, thus ensuring the operational amplifier has extremely low equivalent input voltage noise and current noise.The test results show that the rail-to-rail input/output operational amplifier with this structure has a bandwidth of 5.05 MHz, a large signal low frequency gain of 136.2 dB,a low input bias current of 29.8 nA, an input offset current of 11.9 nA, an input offset voltage of 188 μV, an input voltage noise density of ■ kHz, a common mode rejection ratio(CMRR) of 121.6 dB, and a high power supply rejection ratio(PSRR) of 117.3 dB.