摘要
研究了万兆级别以太网编解码芯片的设计方法,在前端设计中给出了编解码电路的结构图,并对电路进行仿真,得到解码和扰码的仿真波形图;同时给出了后端芯片设计版图结果;最后提出了流片后可行性的测试方案。
In this paper,the design method of 10,000 Mega Ethernet codec chip is studied.The structure of the codec circuit is given in the front-end design,and the simulation waveform of the decoding and scrambling code is obtained by the simulation of the circuit.At the same time,the layout of the back-end chip is given.Finally,the test scheme of the feasibility after streaming is put forward.
出处
《工业控制计算机》
2019年第11期64-64,67,共2页
Industrial Control Computer
关键词
万兆级别
编解码
芯片
gigabit level
coding and decoding
chip
