高性能小数分频锁相环的研究与实现

Research and Implementation of High Performance Fractional PLL

随着集成电路技术的迅猛发展,芯片内时钟信号精度要求越来越高,如何提高时钟信号的品质是集成电路行业的研究重点。小数分频锁相环是时钟信号实现高分辨率、快速变频的常用结构,但是受到自身结构的制约,小数分频锁相环会引入大量杂散噪声,杂散噪声对输出信号影响极大,在设计中消除和抑制杂散噪声成为挑战。论文通过分析小数分频锁相环的基本结构,研究了杂散与噪声种类和来源,解释了杂散与噪声的产生机理,提出了一种基于DAC的噪声补偿技术,设计并实现了一款高性能、低相噪的小数分频锁相环。锁相环分频精度为24位,功耗为3.4mW,面积为0.06mm^2。

With the rapid development of integrated circuit technology,the precision requirement of clock signal in chip is getting higher and higher.How to improve the quality of clock signals is the research focus of the integrated circuit industry.The fractional PLL is a common structure for realizing high-resolution and fast frequency conversion of clock signals.However,due to its own structure,the fractional PLL introduces a lot of stray noise,and the stray noise has a great influence on the output signal.Eliminating and suppressing stray noise in the design becomes a challenge.By analyzing the basic structure of fractional PLL,this paper studies the types and sources of spurs and noise,explains the mechanism of spurs and noise,and proposes a DAC-based noise compensation technique,which designs and implements a high performance,low phase noise fractional PLL.The PLL has a frequency division accuracy of 24 bits,a power consumption of 3.4 mW,a lock time of 1.83μs,and an area of 0.06 mm^2.