薄膜晶体管平坦化层干法刻蚀工艺的研究

Dry etching for the planarization layer of thin film transistors

为了降低薄膜晶体管的寄生电容,一种新型平坦化材料被引入。单独采用反应离子刻蚀(RIE)或增强电容耦合等离子刻蚀(ECCP)模式刻蚀该平坦化层均无法获得满意的工艺效果。为此,提出了将RIE和ECCP相结合的方法用于新型平坦化层的刻蚀。实验结果表明:当平坦化层厚度为2.0μm时,先以RIE模式7 kW/20 Pa条件刻蚀1.5μm,再以ECCP模式5 kW+4 kW/8 Pa条件继续刻蚀平坦化层及其下方的氮化硅,刻蚀出的过孔图形表面光滑,氮化硅层无底切,平坦化层孔径均值6.12μm。本研究结果为后续采用该平坦层材料的高分辨率、低功耗产品的设计和生产打下了坚实基础。

In order to reduce the parasitic capacitances of thin film transistor(TFTs),a new type of planarization material was adopt.However,neither reactive ion etching(RIE)nor enhanced capacitive couple plasma(ECCP)could well etch this film.Accordingly,the combination of RIE and ECCP was proposed to improve the etching effects.When the thickness of planarization layer was 2.0μm,we first etched 1.5μm of the planarization layer by RIE mode(7 kW/20 Pa),then etched the rest as well as the underneath silicon nitride film by ECCP mode(5 kW+4 kW/8 Pa);the surface of via hole was smooth without undercut issue,and the via hole critical dimension(CD)was 6.12μm.These results lay a solid foundation for the design and fabrication of the high-resolution and low-power products with this new planarization layers.