一种高速近似乘法器设计

A High Speed Approximate Multiplier Design

近似计算作为一种有效权衡精度与性能的新型计算方式,已被广泛运用于图像处理、数据挖掘和多媒体技术等能够容忍少量计算错误的相关应用中,然而此类应用存在大量乘法操作。为加快数据处理速度,设计一种新型的近似乘法器,采用近似加法实现部分累加运算,从而减少近似乘法器的资源消耗,同时通过流水线结构增加系统的时钟频率,进而提高数据吞吐率。统计结果表明,与精确乘法器相比,该设计可节省32.2%的查找表资源。在图像处理应用中,相较AMA、UDM等近似乘法器,该设计的峰值信噪比较高,图像重构的效果较好。

Approximate compute,as a new calculation method that effectively balances accuracy and performance,has been widely used in applications such as image processing,data mining,and multimedia technology that can tolerate a small number of computational errors.There is the large number of multiply-accumulate operations in these applications.To speed up data processing,this paper designs a new type of approximate multiplier.The multiplier uses approximate addition to achieve partial accumulation,thus reducing the resource consumption of the approximate multiplier.Besides,a pipeline structure is adopted to increase the clock frequency of the system,thereby,increasing the data throughput.The statistical results show that compared with that of the precision multiplier,the Look-Up-Table(LUT)resource savings of the approximate multiplier reach 32.2%.Also,in image processing applications,compared with AMA,UDM approximate multipliers,the proposed multiplier has higher Peak Signal-to-Noise Ratio(PSNR)and better effect on image reconstruction.