FPGA之基于Verilog语言实现优先抢答锁存模块的实现

Implementation of Priority Answer Lock Module Based on Verilog Language in FPGA

抢答模块和锁存模块的基本实现是抢答器,抢答器是比赛和竞赛中一种常用且必备的装置,其原理是一种非常典型的数字逻辑电路,其中含有时序逻辑电路和基本逻辑电路组成,其项目包含D触发器,锁存器,分频器,7段数码管的译码器,主持人按开始按钮示意开始抢答,本文将使用Verilog HDL语言实现其功能,并通过对抢答器电路设计的分析加深对其功能实现电路的认识和理解。

The basic realization of answering module and locking module is answering machine.Answer scrambler is a common and necessary device in competitions.Its principle is a very typical digital logic circuit,which consists of sequential logic circuit and basic logic circuit.It includes D flip-flop,latch,frequency divider,7-segment digital tube decoder.The host presses the start button to the start scrambling.In this paper,Verilog HDL language is used to analyze the circuit design of the answer,and to make the understanding and comprehension of its functional realization circuit deeply.