一种利用资源协商的FPGA布局方法

Approach to FPGA placement using resource negotiation

由于布局是现场可编程门阵列电路开发流程中耗时最长的步骤之一,所以为了提高布局的速度,提出了一种新的现场可编程门阵列布局方法。首先,在初始布局阶段,电路中的各逻辑单元根据花费计算公式选择使用成本最小的物理资源,并且允许多个逻辑单元占用同一个物理资源;然后,迭代地对占用被重用物理资源的逻辑单元重新布局,通过逐渐增大重用资源的使用成本,从而逐步消除资源重用;最后,用低温模拟退火算法对布局结果进行局部优化。实验结果表明,与学术界主流布局工具相比,该方法将布局时间减少了52%,同时电路延时降低4.8%,总线长减少1.9%。所提布局方法显著地减少了现场可编程门阵列电路布局所需时间,从而缩短了电路编译调试周期,有助于提高开发人员的效率。

Placement is one of the most time-consuming steps of the Field Programmable Gate Array(FPGA)computer aided design flow.In order to accelerate the placement step,a novel approach to FPGA placement is proposed.First,circuit logic blocks choose to use the lowest cost physical resources,and it is allowed that multiple logic blocks share the same resource.Second,the logic blocks using the overused physical resources are re-placed iteratively;the cost of the overused resources is gradually increased,thus eliminating the overuse of the physical resources progressively.Finally,the low-temperature simulated annealing algorithm is applied to optimize the placement result.Experimental results show that the proposed approach reduces the placement runtime by 52%compared with the state-of-the art placement tool,with a reduction of critical path delay and total wirelength by 4.8%and 1.9%,respectively.The proposed approach significantly accelerates the FPGA placement and hence shortens the compile-debug cycle of circuits,which is helpful to improving the efficiency of the developers.