一种65 nm CMOS 60 GHz高增益功率放大器

A 65 nm CMOS 60 GHz High Gain Power Amplifier

设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。

A 60 GHz power amplifier(PA)was designed in a 65 nm CMOS technology.A cascode stage combined with a capacitor-neutralized common-source structure was used to increase the gain of the power amplifier,and a two-pass differential structure was adopted to increase the output power of the power amplifier.On-chip transformers for input/output matching and inter-stage matching were also used to reduce the chip area,thereby reducing costs.Through the co-simulation with Cadence,ADS and Momentum,at the working frequency of 60 GHz,the maximum small signal gain was 26 dB,the maximum power added efficiency(PAE)was 18.6%,and the saturated output power was 15.2 dBm.The proposed power amplifier had the advantages of high gain,high efficiency and low cost,etc.